该文档详细叙述了Intel 5000V,5000P,5000Z芯片的结构，功能及参数
主要内容包括：
1 Introduction
1.1 Terminology
1.2 Related Documents and Materials
1.2.1 BIOS Self-test Utility
1.3 Intel 5000P Chipset Overview
2 Signal Description
2.1 Processor Front Side Bus Signals
2.1.1 Processor Front Side Bus 0
2.1.2 Processor Front Side Bus 1
2.2 Fully Buffered DIMM Memory Channels
2.2.1 FB-DIMM Branch 0
2.2.1.1 FB-DIMM Channel 0
2.2.1.2 FB-DIMM Channel 1
2.2.2 FB-DIMM Branch 1
2.2.2.1 FB-DIMM Channel 2
2.2.2.2 FB-DIMM Channel 3
2.3 PCI Express* Signal List
2.3.1 PCI Express* Common Signals
2.3.2 PCI Express Port 0, Enterprise South Bridge Interface (ESI)
2.3.3 PCI Express Port 2
2.3.4 PCI Express Port 3
2.3.5 PCI Express Port 4
2.3.6 PCI Express Port 5
2.3.7 PCI Express Port 6
2.3.8 PCI Express Port 7
2.4 System Management Bus Interfaces
2.5 XD Port Signal List
2.6 JTAG Bus Signal List
2.7 Clocks, Reset and Miscellaneous
2.8 Power and Ground Signals
2.9 MCH Sequencing Requirements
2.10 Reset Requirements
2.10.1 Timing Diagrams
2.10.1.1 Power-Up
2.10.1.2 Power Good
2.10.1.3 Hard Reset
2.10.1.4 RESETI# Retriggering Limitations
2.10.2 Reset Timing Requirements
2.10.3 Miscellaneous Requirements and Limitations
2.11 Intel 5000P Chipset Platform Signal Routing Topology Diagrams
2.11.1 Intel 5000P Customer Reference Platform (SRP) Reset Topology
2.12 Signals Used as Straps
2.12.1 Functional Straps
3 Register Description
3.1 Register Terminology
3.2 Platform Configuration Structure
3.3 Routing Configuration Accesses
3.3.1 Standard PCI Bus Configuration Mechanism
3.3.2 PCI Bus 0 Configuration Mechanism
3.3.3 Primary PCI and Downstream Configuration Mechanism
3.4 Device Mapping
3.4.1 Device Identification for Intel 5000P Chipset, Intel 5000Z Chipset, and Intel 5000V Chipset Components
3.4.2 Special Device and Function Routing
3.5 I/O Mapped Registers
3.5.1 CFGADR: Configuration Address Register
3.5.2 CFGDAT: Configuration Data Register
3.6 MCH Fixed Memory Mapped Registers
3.7 Detailed Configuration Space Maps
3.8 Register Definitions
3.8.1 PCI Standard Registers
3.8.1.1 VID - Vendor Identification Register
3.8.1.2 DID - Device Identification Register
3.8.1.3 RID - Revision Identification Register
3.8.1.4 CCR - Class Code Register
3.8.1.5 HDR - Header Type Register
3.8.1.6 SVID - Subsystem Vendor Identification Register
3.8.1.7 SID - Subsystem Identity
3.8.2 Address Mapping Registers
3.8.2.1 PAM0 - Programmable Attribute Map Register 0
3.8.2.2 PAM1 - Programmable Attribute Map Register 1
3.8.2.3 PAM2 - Programmable Attribute Map Register 2
3.8.2.4 PAM3 - Programmable Attribute Map Register 3
3.8.2.5 PAM4 - Programmable Attribute Map Registers 4
3.8.2.6 PAM5 - Programmable Attribute Map Register 5
3.8.2.7 PAM6 - Programmable Attribute Map Register 6
3.8.2.8 SMRAMC - System Management RAM Control Register
3.8.2.9 EXSMRC - Extended System Management RAM Control Register
3.8.2.10 EXSMRTOP - Extended System Management RAM Top Register
3.8.2.11 EXSMRAMC - Expansion System Management RAM Control Register
3.8.2.12 HECBASE - PCI Express Extended Configuration Base Address Register
3.8.3 AMB Memory Mapped Registers
3.8.3.1 AMBASE: AMB Memory Mapped Register Region Base Register
3.8.3.2 AMR - AMB Memory Mapped Registers Region Range Register
3.8.3.3 AMBSELECT - AMB Switching Window Select Register
3.8.3.4 MAXCH - Maximum Channel Number Register
3.8.3.5 MAXDIMMPERCH - Maximum DIMM PER Channel Number Register
3.8.3.6 Map to AMB Registers
3.8.4 Interrupt Redirection Registers
3.8.4.1 REDIRCTL - Redirection Control Register
3.8.4.2 REDIRBUCKETS - Redirection Bucket Number Register
3.8.5 Boot and Reset Registers
3.8.5.1 SYRE - System Reset Register
3.8.5.2 CPURSTCAPTMR: CPU Reset Done Cap Latency Timer
3.8.5.3 POC - Power-On Configuration Register
3.8.5.4 SPAD[3:0] - Scratch Pad Registers
3.8.5.5 SPADS[3:0] - Sticky Scratch Pad
3.8.5.6 BOFL[3:0] - Boot Flag Register
3.8.6 Control and Interrupt Registers
3.8.6.1 PROCENABLE: Processor Enable Global Control
3.8.6.2 FSBS[1:0] - Processor Bus Status Register
3.8.6.3 XTPR[7:0] - External Task Priority Register
3.8.7 PCI Express Device Configuration Registers
3.8.8 PCI Express Header
3.8.8.1 PCICMD[7:2, 0]- Command Register
3.8.8.2 PCISTS[7:2, 0] - Status Register
3.8.8.3 CLS[7:2, 0] - Cache Line Size
3.8.8.4 PRI_LT[7:2, 0] - Primary Latency Timer
3.8.8.5 BIST[7:2,0] - Built-In Self Test
3.8.8.6 BAR0[7:2,0] - Base Address Register 0
3.8.8.7 BAR1[7:2,0] - Base Address Register 1
3.8.8.8 EXP_ROM[0]: Expansion ROM Registers
3.8.8.9 PBUSN[7:2] - Primary Bus Number
3.8.8.10 SBUSN[7:2] - Secondary Bus Number
3.8.8.11 SUBUSN[7:2] - Subordinate Bus Number
3.8.8.12 SEC_LT[7:2] - Secondary Latency Timer
3.8.8.13 IOBASE[7:2] - I/O Base Register
3.8.8.14 IOLIM[7:2] - I/O Limit Register
3.8.8.15 SECSTS[7:2] - Secondary Status
3.8.8.16 MBASE[7:2] - Memory Base
3.8.8.17 MLIM[7:2]: Memory Limit
3.8.8.18 PMBASE[7:2] - Prefetchable Memory Base
3.8.8.19 PMLIM[7:2] - Prefetchable Memory Limit
3.8.8.20 PMBU[7:2] - Prefetchable Memory Base (Upper 32 bits)
3.8.8.21 PMLU[7:2] - Prefetchable Memory Limit (Upper 32 bits)
3.8.8.22 IOB[7:2] - I/O Base Register (Upper 16 bits)
3.8.8.23 IOL[7:2] - I/O Limit Register (Upper 16 bits)
3.8.8.24 CAPPTR[7:2, 0]- Capability Pointer
3.8.8.25 RBAR[7:2] - ROM Base Address Register
3.8.8.26 INTL[7:2,0] - Interrupt Line Register
3.8.8.27 INTP[7:2,0] - Interrupt Pin Register
3.8.8.28 BCTRL[7:2] - Bridge Control Register
3.8.8.29 PEXLWSTPCTRL: PCI Express Link Width Strap Control Register
3.8.8.30 PEXCTRL[7,2:0]: PCI EXPRESS Control Register
3.8.8.31 PEXCTRL2[7:2,0]: PCI Express Control Register 2
3.8.8.32 PEXCTRL3[7:2,0] - PCI Express Control Register 3
3.8.8.33 PEXGCTRL - PCI Express Global Control Register
3.8.8.34 INTXSWZCTRL[7:2,0]: PCI Express Interrupt Swizzle Control Register
3.8.9 PCI Express Power Management Capability Structure
3.8.9.1 PMCAP[7:2,0] - Power Management Capabilities Register
3.8.9.2 PMCSR[7:2, 0] - Power Management Control and Status Register
3.8.10 PCI Express Message Signaled Interrupts (MSI) Capability Structure
3.8.10.1 MSICAPID[7:2, 0] - MSI Capability ID
3.8.10.2 MSINXPTR[7:2, 0]- MSI Next Pointer
3.8.10.3 MSICTRL[7:2, 0] - Message Control Register
3.8.10.4 MSIAR[7:2, 0] - MSI Address Register
3.8.10.5 MSIDR[7:2, 0] - MSI Data Register
3.8.11 PCI Express Capability Structure
3.8.11.1 PEXCAPL[7:2, 0]- PCI Express Capability List Register
3.8.11.2 PEXCAP[7:2, 0] - PCI Express Capabilities Register
3.8.11.3 PEXDEVCAP[7:2, 0] - PCI Express Device Capabilities Register
3.8.11.4 PEXDEVCTRL[7:2, 0] - PCI Express Device Control Register
3.8.11.5 PEXDEVSTS[7:2, 0] - PCI Express Device Status Register
3.8.11.6 PEXLNKCAP[7:2,0] - PCI Express Link Capabilities Register
3.8.11.7 PEXLNKCTRL[7:2, 0] - PCI Express Link Control Register
3.8.11.8 PEXLNKSTS[7:2, 0] - PCI Express Link Status Register
3.8.11.9 PEXSLOTCAP[7:2, 0] - PCI Express Slot Capabilities Register
3.8.11.10 PEXSLOTCTRL[7:2, 0] - PCI Express Slot Control Register
3.8.11.11 PEXSLOTSTS[7:2, 0] - PCI Express Slot Status Register
3.8.11.12 PEXRTCTRL[7:2, 0] - PCI Express Root Control Register
3.8.11.13 PEXRTSTS[7:2, 0] - PCI Express Root Status Register
3.8.11.14 ESICTRL[0] - ESI Control Register
3.8.12 PCI Express Advanced Error Reporting Capability
3.8.12.1 PEXENHCAP[7:2, 0] - PCI Express Enhanced Capability Header
3.8.12.2 UNCERRSTS[7:2] - Uncorrectable Error Status
3.8.12.3 UNCERRSTS[0] - Uncorrectable Error Status For ESI Port
3.8.12.4 UNCERRMSK[7:2] - Uncorrectable Error Mask
3.8.12.5 UNCERRMSK[0] - Uncorrectable Error Mask For ESI Port
3.8.12.6 UNCERRSEV[0] - Uncorrectable Error Severity For ESI Port
3.8.12.7 UNCERRSEV[7:2] - Uncorrectable Error Severity
3.8.12.8 CORERRSTS[7:2, 0] - Correctable Error Status
3.8.12.9 CORERRMSK[7:2, 0] - Correctable Error Mask
3.8.12.10 AERRCAPCTRL[7:2, 0] - Advanced Error Capabilities and Control Register
3.8.12.11 HDRLOG0[7:2, 0] - Header Log 0
3.8.12.12 HDRLOG1[7:2, 0] - Header Log 1
3.8.12.13 HDRLOG2[7:2, 0] - Header Log 2
3.8.12.14 HDRLOG3[7:2, 0] - Header Log 3
3.8.12.15 RPERRCMD[7:2, 0] - Root Port Error Command
3.8.12.16 RPERRSTS[7:2, 0] - Root Error Status Register
3.8.12.17 RPERRSID[7:2, 0] - Error Source Identification Register
3.8.12.18 Intel 5000P Chipset MCH SPCAPID[7:2, 0] - MCH Specific Capability ID
3.8.12.19 PEX_ERR_DOCMD[7:2, 0] - PCI Express Error Do Command Register
3.8.12.20 EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI
3.8.12.21 EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask
3.8.12.22 EMASK_COR_PEX[7:2, 0] - Correctable Error Detect Mask
3.8.12.23 EMASK_RP_PEX[7:2, 0] - Root Port Error Detect Mask
3.8.12.24 PEX_FAT_FERR[7:2, 0] - PCI Express First Fatal Error Register
3.8.12.25 PEX_NF_COR_FERR[7:2, 0] - PCI Express First Non-Fatal or Correctable Error Register
3.8.12.26 PEX_FAT_NERR[7:2, 0] - PCI Express Next Fatal Error Register
3.8.12.27 PEX_NF_COR_NERR[7:2, 0] - PCI Express Non Fatal or Correctable Next Error Register
3.8.12.28 PEX_UNIT_FERR[7:2, 0] - PCI Express First Unit Error Register
3.8.12.29 PEX_UNIT_NERR[7:2] - PCI Express Next Unit Error Register
3.8.12.30 PEX_SSERR[7:2,0]: PCI Express Stop and Scream Error Register
3.8.13 Error Registers
3.8.13.1 FERR_GLOBAL - Global First Error Register
3.8.13.2 NERR_GLOBAL - Global Next Error Register
3.8.13.3 FERR_FAT_FSB[1:0]: FSB First Fatal Error Register
3.8.13.4 FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register
3.8.13.5 NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register
3.8.13.6 NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register
3.8.13.7 NRECFSB[1:0]: Non Recoverable FSB Error Log Register
3.8.13.8 RECFSB[1:0]: Recoverable FSB Error Log Register
3.8.13.9 NRECADDRL[1:0]: Non Recoverable FSB Address Low Error Log Register
3.8.13.10 NRECADDRH[1:0]: Non Recoverable FSB Address High Error Log Register
3.8.13.11 EMASK_FSB[1:0]: FSB Error Mask Register
3.8.13.12 ERR2_FSB[1:0]: FSB Error 2 Mask Register
3.8.13.13 ERR1_FSB[1:0]: FSB Error 1 Mask Register
3.8.13.14 ERR0_FSB[1:0]: FSB Error 0 Mask Register
3.8.13.15 MCERR_FSB[1:0]: FSB MCERR Mask Register
3.8.13.16 FERR_FAT_INT - Internal First Fatal Error Register
3.8.13.17 FERR_NF_INT - Internal First Non-Fatal Error Register
3.8.13.18 NERR_FAT_INT - Internal Next Fatal Error Register
3.8.13.19 NERR_NF_INT - Internal Next Non-Fatal Error Register
3.8.13.20 NRECINT - Non Recoverable Internal MCH Error Log Register
3.8.13.21 RECINT - Recoverable Internal MCH Data Log Register
3.8.13.22 EMASK_INT - Internal Error Mask Register
3.8.13.23 ERR2_INT - Internal Error 2 Mask Register
3.8.13.24 ERR1_INT - Internal Error 1 Mask Register
3.8.13.25 ERR0_INT - Internal Error 0 Mask Register
3.8.13.26 MCERR_INT - Internal MCERR Mask Register
3.9 Memory Control Registers
3.9.1 MC - Memory Control Settings
3.9.2 GBLACT - Global Activation Throttle Register
3.9.3 THRTSTS[1:0] - Thermal Throttling Status Register
3.9.4 THRTLOW - Thermal Throttling Low Register
3.9.5 THRTMID - Thermal Throttle Mid Register
3.9.6 THRTHI - Thermal Throttle High Register
3.9.7 THRTCTRL - Thermal Throttling Control Register
3.9.8 MCA - Memory Control Settings A
3.9.9 DDRFRQ - DDR Frequency Ratio
3.9.10 FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio Configuration 0
3.9.11 FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio Configuration 1
3.9.12 HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio Configuration
3.9.13 GRFBDVLDCFG: FB-DIMM Valid Configuration
3.9.14 GRHOSTFULLCFG: Host Full Flow Control Configuration
3.9.15 GRBUBBLECFG: FB-DIMM Host Bubble Configuration
3.9.16 GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double Configuration
3.9.17 Summary of Memory Gearing Register operating modes
3.9.18 DRTA - DRAM Timing Register A
3.9.19 DRTB - DDR Timing Register B
3.9.20 ERRPER - Error Period
3.9.21 Memory Map Registers
3.9.21.1 TOLM - Top Of Low Memory
3.9.21.2 MIR[2:0] - Memory Interleave Range
3.9.21.3 AMIR[2:0] - Adjusted Memory Interleave Range
3.9.22 FB-DIMM Error Registers
3.9.22.1 FERR_FAT_FBD - FB-DIMM First Fatal Errors
3.9.22.2 NERR_FAT_FBD - FB-DIMM Next Fatal Errors
3.9.22.3 FERR_NF_FBD - FB-DIMM First Non-Fatal Errors
3.9.22.4 NERR_NF_FBD - FB-DIMM Next Fatal Errors
3.9.22.5 EMASK_FBD - FB-DIMM Error Mask Register
3.9.22.6 ERR0_FBD: FB-DIMM Error 0 Mask Register
3.9.22.7 ERR1_FBD: FB-DIMM Error 1 Mask Register
3.9.22.8 ERR2_FBD: FB-DIMM Error 2 Mask Register
3.9.22.9 MCERR_FBD - FB-DIMM MCERR Mask Register
3.9.22.10 NRECMEMA - Non-Recoverable Memory Error Log Register A
3.9.22.11 NRECMEMB - Non-Recoverable Memory Error Log Register B
3.9.22.12 NRECFGLOG - Non-Recoverable DIMM Configuration Access Error Log Register
3.9.22.13 NRECFBDA: Non-Recoverable FB-DIMM Error Log Register A
3.9.22.14 NRECFBDB - Non-Recoverable FB-DIMM Error Log Register B
3.9.22.15 NRECFBDC - Non-Recoverable FB-DIMM Error Log Register C
3.9.22.16 NRECFBDD - Non-Recoverable FB-DIMM Error Log Register D
3.9.22.17 NRECFBDE - Non-Recoverable FB-DIMM Error Log Register E
3.9.22.18 REDMEMB: Recoverable Memory Data Error Log Register B
3.9.22.19 RECMEMA - Recoverable Memory Error Log Register A
3.9.22.20 RECMEMB - Recoverable Memory Error Log Register B
3.9.22.21 RECFGLOG - Recoverable DIMM Configuration Access Error Log Register
3.9.22.22 RECFBDA - Recoverable FB-DIMM Error Log Register A
3.9.22.23 RECFBDB - Recoverable FB-DIMM Error Log Register B
3.9.22.24 RECFBDC - Recoverable FB-DIMM Error Log Register C
3.9.22.25 RECFBDD - Recoverable FB-DIMM Error Log Register D
3.9.22.26 RECFBDE - Recoverable FB-DIMM Error Log Register E
3.9.23 FB-DIMM Branch Registers
3.9.23.1 FBDLVL[1:0][1:0] - FB-DIMM Packet Levelization
3.9.23.2 FBDHPC[1:0]: FBD State Control
3.9.23.3 FBDST[1:0] - FB-DIMM Status
3.9.23.4 FBDRST[1:0] - FB-DIMM Reset
3.9.23.5 SPCPC[1:0] - Spare Copy Control
3.9.23.6 SPCPS[1:0] - Spare Copy Status
3.9.23.7 MTR[1:0][3:0] - Memory Technology Registers
3.9.23.8 DMIR[1:0][4:0] - DIMM Interleave Range
3.9.23.9 FBDICMD[1:0][1:0] - FB-DIMM Initialization Command
3.9.23.10 FBDISTS[1:0][1:0] - FB-DIMM Initialization Status
3.9.23.11 AMBPRESENT[1:0][1:0] - FB-DIMM AMB Slot Present Register
3.9.24 FB-DIMM RAS Registers
3.9.24.1 UERRCNT[1:0] - Uncorrectable Error Count
3.9.24.2 CERRCNT[1:0] - Correctable Error Count
3.9.24.3 BADRAMA[1:0] - Bad DRAM Marker A
3.9.24.4 BADRAMB[1:0] - Bad DRAM Marker B
3.9.24.5 BADCNT[1:0] - Bad DRAM Counter
3.9.24.6 FBDSBTXCFG[1:0][1:0]: FB-DIMM Southbound Transmit Configuration Register
3.9.25 FB-DIMM IBIST Registers
3.9.25.1 FBD[3:2]IBPORTCTL: FB-DIMM IBIST Port Control Register
3.9.25.2 FBD[1:0]IBPORTCTL: FB-DIMM IBIST Port Control Register
3.9.25.3 FBD[3:2]IBTXPGCTL: FB-DIMM IBIST Pattern Generator Control Register
3.9.25.4 FBD[1:0]IBTXPGCTL: FB-DIMM IBIST Pattern Generator Control Register
3.9.25.5 FBD[3:2]IBPATBUF: FB-DIMM IBIST Pattern Buffer Register
3.9.25.6 FBD[1:0]IBPATBUF: FB-DIMM IBIST Pattern Buffer Register
3.9.25.7 FBD[3:2]IBTXMSK: IBIST Transmitter Mask
3.9.25.8 FBD[1:0]IBTXMSK: IBIST Transmitter Mask
3.9.25.9 FBD[3:2]IBRXMSK: IBIST Receiver Mask
3.9.25.10 FBD[1:0]IBRXMSK: IBIST Receiver Mask
3.9.25.11 FBD[3:2]IBTXSHFT: IBIST Transmit Shift Inversion Register
3.9.25.12 FBD[1:0]IBTXSHFT: IBIST Transmit Shift Inversion Register
3.9.25.13 FBD[3:2]IBRXSHFT: IBIST Receive Shift Inversion Register
3.9.25.14 FBD[1:0]IBRXSHFT: IBIST Receive Shift Inversion Register
3.9.25.15 FBD[3:2]LNERR: IBIST Receive Lane Error Register
3.9.25.16 FBD[1:0]LNERR: IBIST Receive Lane Error Register
3.9.25.17 FBD[3:2]IBRXPGCTL: FB-DIMM IBIST Rx Pattern Generator Control Register
3.9.25.18 FBD[1:0]IBRXPGCTL: FB-DIMM IBIST Rx Pattern Generator Control Register
3.9.25.19 FBD[3:2]IBPATBUF2: FB-DIMM IBIST Pattern Buffer 2 Register
3.9.25.20 FBD[1:0]IBPATBUF2: FB-DIMM IBIST Pattern Buffer 2 Register
3.9.25.21 FBD[3:2]IBTXPAT2EN: IBIST TX Pattern Buffer 2 Enable
3.9.25.22 FBD[1:0]IBTXPAT2EN: IBIST TX Pattern Buffer 2 Enable
3.9.25.23 FBD[3:2]IBRXPAT2EN: IBIST RX Pattern Buffer 2 Enable
3.9.25.24 FBD[1:0]IBRXPAT2EN: IBIST RX Pattern Buffer 2 Enable
3.9.26 Serial Presence Detect Registers
3.9.26.1 SPD[1:0][1:0] - Serial Presence Detect Status Register
3.9.26.2 SPDCMD[1:0][1:0] - Serial Presence Detect Command Register
3.10 DMA Engine Configuration Registers
3.10.1 PCICMD: PCI Command Register
3.10.2 PCISTS: PCI Status Register
3.10.3 CCR: Class Code Register
3.10.4 CB_BAR: DMA Engine Base Address Register
3.10.5 CAPPTR: Capability Pointer Register
3.10.6 INTL: Interrupt Line Register
3.10.7 INTP: Interrupt Pin Register
3.10.8 Power Management Capability Structure
3.10.8.1 PMCAP - Power Management Capabilities Register
3.10.8.2 PMCSR - Power Management Control and Status Register
3.10.9 MSICAPID - Message Signalled Interrupt Capability ID Register
3.10.10 MSINXPTR - Message Signalled Interrupt Next Pointer Register
3.10.11 MSICTRL - Message Signalled Interrupt Control Register
3.10.12 MSIAR: Message Signalled Interrupt Address Register
3.10.13 MSIDR: Message Signalled Interrupt Data Register
3.10.14 PEXCAPID: PCI Express Capability ID Register
3.10.15 PEXNPTR: PCI Express Next Pointer Register
3.10.16 PEXCAPS - PCI Express Capabilities Register
3.10.17 PEXDEVCAP - Device Capabilities Register
3.10.18 PEXDEVCTRL - Device Control Register
3.10.19 PEXDEVSTS - PCI Express Device Status Register
3.11 PCI Express IBIST Registers
3.11.1 DIOIBSTR: PCI Express IBIST Global Start/Status Register
3.11.2 DIO0IBSTAT: PCI Express IBIST Completion Status Register
3.11.3 DIO0IBERR: PCI Express IBIST Error Register
3.11.4 PEX[7:2,0]IBCTL: PEX IBIST Control Register
3.11.5 PEX[7:2,0]IBSYMBUF: PEX IBIST Symbol Buffer
3.11.6 PEX[7:2,0]IBEXTCTL: PEX IBIST Extended Control Register
3.11.7 PEX[7:2,0]IBDLYSYM: PEX IBIST Delay Symbol
3.11.8 PEX[7:2,0]IBLOOPCNT: PEX IBIST Loop Counter
3.11.9 PEX[7:2,0]IBLNS[3:0]: PEX IBIST Lane Status
3.11.10 DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count
4 System Address Map
4.1 System Memory Address Ranges
4.1.1 32/64-bit addressing
4.2 Compatibility Area
4.2.1 MS-DOS Area (0 0000h-9 FFFFh)
4.2.2 Legacy VGA Ranges (A 0000h-B FFFFh)
4.2.3 Expansion Card BIOS Area (C 0000h-D FFFFh)
4.2.4 Lower System BIOS Area (E 0000h-E FFFFh)
4.2.5 Upper System BIOS Area (F 0000h-F FFFFh)
4.3 System Memory Area
4.3.1 System Memory
4.3.2 15 MB - 16 MB Window (ISA Hole)
4.3.3 Extended SMRAM Space (TSEG)
4.3.4 Memory Mapped Configuration (MMCFG) Region
4.3.5 Low Memory Mapped I/O (MMIO)
4.3.6 Chipset Specific Range
4.3.7 Interrupt/SMM Region
4.3.7.1 I/O APIC Controller Range
4.3.7.2 High SMM Range
4.3.7.3 Interrupt Range
4.3.7.4 Reserved Ranges
4.3.7.5 Firmware Range
4.3.8 High Extended Memory
4.3.8.1 System Memory
4.3.8.2 High MMIO
4.3.8.3 Extended Memory
4.3.9 Main Memory Region
4.3.9.1 Application of Coherency Protocol
4.3.9.2 Routing Memory Requests
4.4 Memory Address Disposition
4.4.1 Registers Used for Address Routing
4.4.2 Address Disposition for Processor
4.4.2.1 Access to SMM Space (Processor Only)
4.4.3 Inbound Transactions
4.5 I/O Address Map
4.5.1 Special I/O Addresses
4.5.2 Outbound I/O Access
4.5.2.1 Outbound I/O Accesses Routing
4.6 Configuration Space
4.7 I/O Address Map
4.7.1 Special I/O Addresses
4.7.2 Outbound I/O Access
4.8 Configuration Space
5 Functional Description
5.1 Processor Front Side Buses
5.1.1 FSB Overview
5.1.2 FSB Dynamic Bus Inversion
5.1.3 FSB Interrupt Overview
5.1.3.1 Upstream Interrupt Messages
5.2 System Memory Controller
5.2.1 Memory Population Rules
5.2.1.1 Non-Mirrored Mode Memory Upgrades
5.2.1.2 Mirrored Mode Memory Upgrades
5.2.2 Fully Buffered DIMM Technology and Organization
5.2.3 FB-DIMM Memory Operating Modes
5.2.3.1 Non-Mirrored Mode Operation
5.2.3.2 Mirrored Mode Operation
5.2.3.3 Mirrored Mode ECC
5.2.3.4 Memory Sparing
5.2.4 Data Poisoning in Memory
5.2.5 Patrol Scrubbing
5.2.6 Demand Scrubbing
5.2.7 x8 Correction
5.2.7.1 Normal
5.2.7.2 Enhanced
5.2.8 Single Device Data Correction (SDDC) Support
5.2.9 FB-DIMM Memory Configuration Mechanism
5.2.10 FB-DIMM Memory Failure Isolation Mechanisms
5.2.10.1 FB-DIMM Configuration Read Error
5.2.10.2 DIMM Failure Isolation
5.2.10.3 ECC Code
5.2.10.4 Inbound ECC Code Layout for Dual-Channel Branches
5.2.10.5 ECC Code Layout for a Single-Channel Branch
5.2.11 DDR2 Protocol
5.2.11.1 Posted CAS
5.2.11.2 Refresh
5.2.11.3 Access Size
5.2.11.4 Transfer Mode
5.2.11.5 Invalid and Unsupported DDR Transactions
5.2.12 Memory Thermal Management
5.2.12.1 Closed Loop Thermal Activate Throttle Control
5.2.12.2 Sequence of Actions During Throttling
5.2.12.3 CKE State Near End of Activation Throttling Window
5.2.12.4 Refresh Handling During Throttling
5.2.12.5 Throttling Parameters for Activation Throttling.
5.2.12.6 Closed Loop Activation Throttling Policy
5.2.12.7 Open Loop Global Throttling
5.2.12.8 Global Activation Throttling Software Usage
5.2.12.9 Dynamic Update of Thermal Throttling Registers
5.2.12.10 General Software Usage Assumptions
5.2.12.11 Dynamic Change Operation Requirements for Open Loop Thermal Thottling (OLTT)
5.2.12.12 Dynamic Change Operation Requirements for Closed Loop Thermal Thottling (CLTT)
5.2.12.13 Disabling Closed/Open Loop Throttling
5.2.13 Electrical Throttling
5.3 Intel 5000P Chipset Behavior on Overtemp State in AMB
5.4 Interrupts
5.5 XAPIC Interrupt Message Delivery
5.5.1 XAPIC Interrupt Message Format
5.5.2 XAPIC Destination Modes
5.5.2.1 Physical Destination Mode (XAPIC)
5.5.2.2 Logical Destination Mode (XAPIC)
5.5.2.3 XAPIC Interrupt Routing
5.5.3 Interrupt Redirection
5.5.3.1 XTPR Registers
5.5.3.2 Redirection Algorithm
5.5.4 EOI
5.6 I/O Interrupts
5.6.1 Ordering
5.6.2 Hardware IRQ IOxAPIC Interrupts
5.6.3 Message Signalled Interrupts
5.6.4 Non-MSI Interrupts - “Fake MSI”
5.7 Interprocessor Interrupts (IPIs)
5.7.0.1 IPI Ordering
5.8 Chipset Generated Interrupts
5.8.1 Intel 5000P Chipset Generation of MSIs
5.8.1.1 MSI Ordering in Intel 5000P Chipset MCH
5.9 Legacy/8259 Interrupts
5.10 Interrupt Error Handling
5.11 Enterprise South Bridge Interface (ESI)
5.11.1 Power Management Support
5.11.1.1 Rst_Warn and Rst_Warn_Ack
5.11.1.2 STPCLK Propagation
5.11.2 Special Interrupt Support
5.11.3 Inbound Interrupts
5.11.4 Legacy Interrupt Messages
5.11.5 End-of-Interrupt (EOI) Support
5.11.6 Error Handling
5.11.6.1 Inbound Errors
5.11.6.2 Outbound Errors
5.12 PCI Express Ports
5.12.1 Intel 5000P Chipset MCH PCI Express Port Overview
5.12.2 Enterprise South Bridge Interface (ESI)
5.12.3 PCI Express Ports 2 and 3
5.12.4 PCI Express General Purpose Ports
5.12.5 Supported Length Width Port Partitioning
5.12.6 PCI Express Port Support Summary
5.12.7 PCI Express Port Physical Layer Characteristics
5.12.7.1 PCI Express Training
5.12.7.2 8b/10b Encoder/Decoder and Framing
5.12.7.3 Elastic Buffers
5.12.7.4 Deskew Buffer
5.12.7.5 Polarity Inversion
5.12.8 Link Layer
5.12.8.1 Data Link Layer Packets (DLLP)
5.12.8.2 ACK/NAK
5.12.8.3 Link Level Retry
5.12.8.4 ACK Time-out
5.12.9 Flow Control
5.12.9.1 Credit Update Mechanism, Flow Control Protocol (FCP)
5.12.10 Transaction Layer
5.13 Power Management
5.13.1 Supported ACPI States
5.13.2 FB-DIMM Thermal Management
5.13.3 FB-DIMM Thermal Diode Overview
5.14 System Reset
5.14.1 MCH Power Sequencing
5.14.2 MCH Reset Types
5.14.2.1 Power-Good Mechanism
5.14.2.2 Hard Reset Mechanism
5.14.2.3 Processor-Only Reset Mechanism
5.14.3 Targeted Reset Mechanism
5.14.4 BINIT# Mechanism
5.14.5 Reset Sequencing
5.15 SMBus Interfaces Description
5.15.1 Internal Access Mechanism
5.15.2 SMBus Transaction Field Definitions
5.15.2.1 Command Field
5.15.2.2 Byte Count Field
5.15.2.3 Address Byte 3 Field
5.15.2.4 Address Byte 2 Field
5.15.2.5 Address Byte 1 Field
5.15.2.6 Address Byte 0 Field
5.15.2.7 Data Field
5.15.2.8 Status Field
5.15.2.9 Unsupported Access Addresses
5.15.3 SMB Transaction Pictographs
5.15.4 Slave SM Bus, SM Bus 0
5.15.4.1 Supported SMBus Commands
5.15.4.2 Configuration Register Read Protocol
5.15.4.3 Configuration Register Write Protocol
5.15.4.4 SMBus Error Handling
5.15.4.5 SMBus Interface Reset
5.15.5 FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4
5.15.5.1 SPD Asynchronous Handshake
5.15.5.2 Request Packet for SPD Random Read
5.15.5.3 Request Packet for SPD Byte Write
5.15.5.4 SPD Protocols
5.15.5.5 SPD Bus Time-out
5.15.6 PCI Express Hot-Plug Support, SM Bus 6
5.15.6.1 Hot-Plug Indicators
5.15.6.2 Attention Button
5.15.7 Hot-Plug Controller
5.15.8 PCI Express Hot-Plug Usage Model
5.15.9 Virtual Pin Ports
5.16 Clocking
5.16.1 Reference Clocks
5.16.2 JTAG
5.16.3 SMBus Clock
5.16.4 GPIO Serial Bus Clock
5.16.5 Clock Pins
5.16.6 High Frequency Clocking Support
5.16.6.1 Spread Spectrum Support
5.16.6.2 Stop Clock
5.16.6.3 Jitter
5.16.6.4 External Reference
5.16.6.5 PLL Lock Time
5.16.6.6 Other PLL Characteristics
5.16.6.7 Analog Power Supply Pins
5.16.6.8 I/O Interface Metastability
5.17 Error List
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
6.1.1 Thermal Characteristics
6.1.2 Power Characteristics
6.2 DC Characteristics
6.2.1 Clock DC Characteristics
6.2.2 FSB Interface DC Characteristics
6.2.3 FB-DIMM DC Characteristics
6.2.4 PCI Express/ ESI Interface DC Characteristics
6.2.5 Miscellaneous DC Characteristics
7 Intel® 5000V Chipset Differences
7.1 Intel 5000V Chipset Overview
7.2 Fully Buffered DIMM (FB-DIMM) Memory
7.3 ESI Port
7.4 PCI Express Ports
7.5 System Management Bus Interfaces
8 Testability
8.1 JTAG Port
8.1.1 JTAG Access to Configuration Space
8.1.2 TAP Signals
8.1.3 Accessing the TAP Logic
8.1.4 Reset Behavior of the TAP
8.1.5 Clocking the TAP
8.1.6 Accessing the Instruction Register
8.1.7 Accessing the Data Registers
8.1.8 Public TAP Instructions
8.1.9 Public Data Instructions
8.1.10 Public Data Register Control
8.1.11 Bypass Register
8.1.11.1 Bypass Register Definition
8.1.12 Device ID Register
8.1.12.1 Device ID Register
8.1.13 Boundary Scan Register
8.2 Extended Debug Port (XDP)
9 Intel® 5000Z Chipset Differences
9.1 Intel 5000Z Chipset Overview
9.2 Fully Buffered DIMM (FB-DIMM) Memory
9.3 ESI Port
9.4 PCI Express Ports
9.5 Register Definitions
9.6 System Management Bus Interfaces
10 Ballout and Package Information
10.1 Intel 5000P Chipset MCH Ballout
10.2 Intel 5000V Chipset MCH Ballout
10.3 Package Information
11 Ballout and Package Information
11.1 Intel 5000Z Chipset MCH Ballout
11.2 Package Information |
2009 APX Technology LLC | About APX | Contact Us | Privacy Policy | Legal